1. Field of the Invention
The invention relates to a wiring board and a process for producing the same, and more particularly to a technique which can be effectively applied to a wiring board having a microstrip structure comprising: a signal wiring layer provided on one main surface of an insulating layer; and a ground layer or a power supply layer provided on another main surface opposite to the main surface on which the signal wiring layer in the insulating layer has been provided.
2. Prior Art
In a conventional BGA (ball grid array) semiconductor device, as shown in FIGS. 1A and 1B, a semiconductor chip 7 is mounted on a wiring board (an interposer) comprising a conductor wiring 201 having a predetermined pattern provided on the surface of an insulating substrate 1.
In the case of a semiconductor device as shown in FIGS. 1A and 1B, in the wiring board, the conductor wiring 201 is provided on the insulating substrate 1 formed of, for example, a thin polyimide tape having a thickness of about 20 to 50 μm. Due to this structure, the strength is low, and deformation is likely to occur in a region on the outer side of a region in which the semiconductor chip 7 has been mounted. To solve this problem, for example, as shown in FIG. 1B, the structure is reinforced, for example, with a metallic cover plate 10.
Further, the wiring board for use in the BGA semiconductor device is used, for example, for matching between an external terminal (a bonding pad) of the semiconductor chip 7 and a terminal (wiring) on a mounting substrate for mounting thereon the semiconductor device, or for grid conversion. As shown in FIG. 2, a first conductor layer M1 is provided on an insulating layer B1, constituted by the insulating substrate 1, in its surface on which the semiconductor chip 7 is mounted, and a second conductor layer M2 is provided on the insulating substrate 1 in its surface opposite to the surface on which the first conductor layer M1 has been provided. In this case, as shown in FIGS. 2 and 3, on the first conductor layer M1 are provided a conductor wiring 201A for providing a power supply of ground potential to the semiconductor chip 7 (hereinafter referred to as “ground wiring”), a conductor wiring 201B for providing an operation power supply of a potential other than the ground potential to the semiconductor chip 7 (hereinafter referred to as “power supply wiring”), and a conductor wiring 201C for transmitting an electric signal (hereinafter referred to as “signal wiring”). Further, in this case, the ground potential is a ground reference potential, and a power supply of 0 (zero) volt (V) or a predetermined potential is provided.
Further, a solder protective, film (a solder resist) 5 is provided on the surface of the first conductor layer M1 so that a portion, to be connected to an external electrode in the semiconductor chip 7, in each of the ground wiring 201A, the power supply wiring 201B, and the signal wiring 201C is opened. A terminal plating 6, such as a gold plating, is provided in the opening in the solder protective film 5.
As shown in FIGS. 2 and 4, a connection terminal 202A to be connected to the ground wiring 201A (hereinafter referred to as “ground terminal”), a connection terminal 202B to be connected to the power supply wiring 201B (hereinafter referred to as “power supply terminal”), and a connection terminal 202C to be connected to the signal wiring 201C (hereinafter referred to as “signal terminal”) are provided, as external connection terminals to be connected to the terminals on the mounting substrate, in the second conductor layer M2 on the insulating substrate 1 in its surface opposite to the surface on which the semiconductor chip 7 is to be mounted. An electrolytic copper plating 3 is provided on the surface of each of the ground terminal 202A, the power supply terminal 202B, and the signal terminal 202C. Further, the electrolytic copper plating 3 is also provided on the inner wall of openings (via holes) VH provided at the predetermined position of the insulating substrate 1. Each conductor wiring in the first conductor layer M1 is electrically connected to a predetermined external connection terminal in the second conductor layer M2 through the electrolytic copper plating (via) within the via hole VH. Specifically, the ground wiring 201A is connected to the ground terminal 202A through a via 3A, the power supply wiring 201B is connected to the power supply terminal 202B through a via 3B, and the signal wiring 201C is connected to the signal terminal 202C through a via 3C.
Further, in this case, the ground terminal 202A and the power supply terminal 202B are provided in a small wiring length so as to minimize the influence of voltage drop or the like attributable to a long path to a corresponding external terminal in the semiconductor chip 7. For example, they are provided on the inside of the signal terminal 202C and within a region in which the semiconductor chip 7 is mounted.
Further, a solder protective film (a solder resist) 5 is provided on the surface of the second conductor layer M2 so that a region L3, to which a ball terminal 11 is to be connected, on the ground terminal 202A, the power supply terminal 202B, and the signal terminal 202C is opened. As shown in FIG. 20, a terminal plating 6, such as a gold plating, is provided in the region L3 to which the ball terminal 11 is to be connected.
For the BGA semiconductor device as shown in FIGS. 1A and 1B, due to a recent tendency toward higher speed (higher frequency) of the operation, the impedance control of each conductor wiring provided on the wiring board used in the semiconductor device, particularly the signal wiring 201C, has become more and more important. To meet this demand, as shown in FIGS. 2 and 4, the ground terminal 202A is provided so as to extend to the whole area of the region except for the circumference of the power supply terminal 202B and the signal terminal 202C to constitute a microstrip structure.
When the density of the signal wiring 201C is increased and the conductor pitch or conductor spacing is reduced, in the transmission of a high frequency signal, resonance between adjacent signal wirings or mutual inductance cause noise in a signal being transmitted through the signal wiring 201C. As a result, the signal waveform is lost. The adoption of the microstrip structure formed by extending the ground terminal 202A to the whole area of the insulating substrate 1 can prevent a deterioration in high frequency characteristics of electric signals, because an eddy current flows, in the ground terminal 202A, in such a direction that bucks a magnetic flux caused by current which flows through each signal wiring to apparently reduce self-inductance of the signal wiring, mutual inductance between signal wirings, or inductive crosstalk.
In the prior art techniques, however, in the microstrip structure formed by extending the ground terminal 202A to the whole area of the insulating substrate 1, the power supply terminal 202B and the signal terminal 202C are also provided in the second conductor layer M2, that is, on the insulating substrate 1 in its surface provided with the ground terminal 202A. Therefore, as shown in FIG. 4, the ground terminal 202A is provided in a pattern such that the circumference of the power supply terminal 202B, the via 3B the via 3B for connecting the power supply wiring 201B to the power supply terminal 202B, the signal terminal 202C, and the via 3C for connecting the signal wiring 201C to the signal terminal 202C is opened.
When a reduction in size of the wiring board or an increase in density of conductor wirings provided on the wiring boards is contemplated, or when the number of the external connection terminals is increased, for example, as a result of higher function of the semiconductor chip, as shown in FIG. 3, in order to allow the power supply terminals 202B and the signal terminals 202C come close to each other as much as possible, a section L4, in which the signal wiring 201C passes over the power supply terminal 202B or the signal terminal 202C, is disadvantageously formed.
When the section L4, in which the signal wiring 201C partially passes over the power supply terminal 202B or the signal wiring 202C, exists, unlike the section in which the wiring passes over the ground terminal 202A, the microstrip effect is unsatisfactory in the section L4. For this reason, in controlling the characteristic impedance of the signal wiring 201C, the distribution of the section L4 should be taken into consideration, disadvantageously making it difficult to control the impedance.
Further, when the section L4, in which the signal wiring 201C passes over the power supply terminal 202B or the signal terminal 202C, exists, in the section L4, noise is likely to occur in the electric signal being transmitted through the signal wiring 201C, and, thus, the characteristics of high frequency signals being transmitted through the signal wiring 201C are disadvantageously likely to be deteriorated.